Verification Design Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to AI-powered systems. We lead in chip design, verification, and IP integration, empowering innovators to create high-performance silicon and software solutions. Join us and help shape the future of technology.

A highly experienced design verification engineer with deep expertise in verifying complex digital IP and high-speed interfaces. You bring strong experience in SystemVerilog, UVM, coverage-driven verification, and debug, along with knowledge of technologies such as DDR, UCIe, PHY, or SERDES. You thrive on solving complex verification challenges and driving high-quality IP from initial architecture through verification closure.

• Develop and execute verification strategies for PHY, DDRIO, UCIe, and other high-speed interface IP.
• Architect and develop SystemVerilog/UVM testbenches, verification environments, test plans, and reusable verification components.
• Create directed and constrained-random tests, assertions, functional coverage, and coverage models.
• Drive functional and code coverage closure, regression analysis, and verification signoff.
• Debug complex RTL, protocol, testbench, and system-level issues in partnership with design engineers.
• Verify block- and subsystem-level functionality, including interfaces, resets, clocking, low-power behavior, and error scenarios.
• Collaborate closely with RTL design, architecture, firmware, modeling, and implementation teams.
• Mentor engineers and help drive verification methodology and best practices.

• Ensure the quality and robustness of next-generation high-speed connectivity IP.
• Identify complex functional and protocol issues early in the development cycle.
• Improve verification efficiency, coverage, reuse, and overall product quality.
• Contribute to industry-leading PHY and interface IP used in advanced semiconductor products.
• Strengthen verification methodologies and technical expertise across the engineering organization.

• BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience, or MS with 10+ years of experience.
• Strong experience in ASIC/IP design verification.
• Advanced proficiency with SystemVerilog and UVM.
• Experience developing verification environments, test plans, assertions, functional coverage, and constrained-random tests.
• Strong RTL and waveform debugging skills.
• Experience with PHY, DDR/DDRIO, UCIe, SERDES, PCIe, CXL, or similar high-speed interface technologies.
• Understanding of the complete ASIC/IP development and verification lifecycle.
• Strong analytical, problem-solving, and communication skills.

• Experience verifying complex IP at the block and subsystem level.
• Experience with coverage-driven verification and verification closure.
• Familiarity with low-power verification, clock/reset verification, and protocol checking.
• Experience with industry-standard simulation, debug, coverage, and verification tools.
• Experience mentoring engineers or providing technical verification leadership.

• A verification engineer who enjoys finding difficult corner cases before they become silicon issues.
• A strong debugger who can work across RTL, testbench, protocol, and system boundaries.
• A collaborative technical partner to design and architecture teams.
• A self-starter who can independently drive verification from planning through closure.
• A mentor who raises the technical capability of the broader team.

You will join a team developing next-generation PHY and high-speed interface IP. Working closely with architecture, RTL design, verification, and implementation teams, you will help ensure complex IP meets demanding functional, performance, and quality requirements.

Synopsys offers a comprehensive and competitive benefits package designed to support your health, wellbeing, and financial future. Your recruiter can provide additional details regarding compensation, benefits, and total rewards during the hiring process.