New

Principle DSP Engineer

Marvell Semiconductor, Inc.
paid time off, flex time, 401(k)
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Jul 09, 2025
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is a leading provider of innovative wireline Commnication technologies, including high-speed inter-connect receivers and Ethernet PHY. The DSP/architecture team is working on the most advanced architectures for PHYs for solutions from 10Mbps to 400Gbps at Data Center and Enterprise. What You Can Expect Design and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designers. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Perform research activities in digital signal processing forBase-T, SerDes and optical channels Work with designers to ensure circuit architecture can be efficiently implemented. Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers. Provide guidance on test plans for lab characterization once design comes back from fab. Participate in chip lab bring up. Should be comfortable working with lab equipment. What We're Looking For Strong knowledge of communications theory, system design and digital signal processing. Proficient in C/C++ and Matlab or Python Familiarity with Ethernet systems is a plus. Experience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR) or FEC (RS, soft decoding, Viterbi algorithm) is a big plus. Experience with ADC-based wireline transceivers and/or coherent DSP architectures is a plus. * Familiarity with fixed-point modeling using Matlab/C/C++ and performance evaluation. * Experience with scripting languages such as Perl/Python is a plus. * Experience in working with Analog design team on AFE modeling is a plus * Experience in working with ASIC design team to guide RTL implementation, verification and validation is a plus Other Skills: * Effective interpersonal and teamwork skills. * Good analysis and problem-solving skills. * Ability to multi-task in a fast-paced environment. Education: * Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience. Expected Base Pay Range (USD) 154,240 - 231,000, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. #LI-TM1