ASIC Engineering Technical Leader

Cisco Systems, Inc.
United States, California, San Jose
170 W Tasman Dr (Show on map)
May 24, 2025
The application window is expected to close on: June 29th, 2025 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. he Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Meet the Team Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world. You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact: You will gain hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation. You will: Architect block, cluster and top level DV environment infrastructure Create DV infrastructure from scratch for block, cluster and top level environments Maintain existing DV environments and enhance them for new features and requirements Ensure complete verification coverage through implementation and review of code and functional coverage Work closely with designers Support tests done with emulation Work closely with software teams and debug issues found during firmware development and be responsible for ASIC bring up Minimum Qualifications: 10+ years ASIC design verification experience with a bachelor's or master's degree Prior experience with ASIC verification using UVM/System Verilog. Prior experience in verifying complex blocks, clusters and top level for SoC Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. Prior experience with cross-functional teams, and possess the drive to learn and grow Prior experience on one or more protocols - PCIe, Ethernet, RDMA, TCP Preferred Qualifications: Prior experience leading a team of engineers to complete verification of a complex block, cluster or chip-level design Lead verification for a complete SOC or ASIC i Prior Experience with Forwarding logic/Parsers/P4 Formal verification (iev/vc formal) knowledge Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.